Measurement Results of Multiple Cell Upsets on a 65nm Tapless Flip-Flop Array

We measured single event upsets (SEUs) and multiple cell upsets (MCUs) of a flip-flop array in a 65nm bulk CMOS process using accelerated white neutron beams. The flipflop array embeds 84,000 FFs constructing a 84,000bit shift register. Its cell structure is so-called tapless, in which no standard cell contains any well tap. Measurement results from 26 DUTs including 2.2Mbit FFs show that both SEUs and MCUs are observed on the tapless structure. MCUs are only observed when master or slave latch stores a specific value. The ratio between SEU rates of master and slave latches from measurements are well consistent with that from circuit-level simulations. SEU rates are almost constant despite the distance from tap, while MCU rates highly depend on it. The FFs farthest from the well tap are 1.6x and 3.7x more vulnerable than the nearest FFs when master and slave latches are in the latch state respectively. We also propose a layout structure to protect an MCU of three FFs in the TMR structure.